Design And Performance Investigation Of Fault Tolerant Quadded Logic With Multi Voltage Logic

As the most quantitative measures of VLSI performance have improved by many orders of magnitude and it has been achieved by the unabated scaling of the sizes of MOSFETs. However, scaling also exacerbates fault, noise and reliability issues, thus posing new challenges in digital circuit design and system. Reliability becomes a major concern due to many and often correlated factors, such as parameter and/or manufacturing variations, aging and soft errors. A Defect and/or fault tolerance may be necessary at several levels throughout the system to improve the reliability of the system. Generally TMR and TIR are used as a fault tolerance technique that produce lower reliability because it depends on number of module and single error affects the multiple modules. Quadded logic (QL) with Quadded transistor (QT) was introduced as a fault tolerance technique. Quadded logic (QL) is an interwoven redundant logic technique that corrects errors by switching them from critical to subcritical status while Quadded Transistor (QT) corrects errors while performing the function of a circuit. The Quadded logic (QL) with Quadded transistor (QT) technique improve reliability than TMR and TIR. By using QLQT speed of operation gets reduced and delay is increased. To increase speed and reduce delay multi voltage logic and dynamic voltage and frequency scaling is proposed. The proposed technique with Quadded logic (QL) Quadded transistor (QT) technique will implemented in half adder. The proposed technique improve reliability and reduce power dissipation. The proposed technique is simulated by using Tina simulator. Keywords-Quadded logic; Quadded Transistor; Multi voltage logic.